NAND flash memories are becoming the predominant technology in the implementation of mass storagesystems for both embedded and high-performance applications. However, when considering data and codestorage in non-volatile memories (NVMs), such as NAND flash memories, reliability and performance becomea serious concern for systems’ designer. Designing NAND flash based systems based on worst-casescenarios leads to waste of resources in terms of performance, power consumption, and storage capacity.This is clearly in contrast with the request for run-time reconfigurability, adaptivity, and resource optimizationin nowadays computing systems. There is a clear trend toward supporting differentiated access modesin flash memory controllers, each one setting a differentiated trade-off point in the performance-reliabilityoptimization space. This is supported by the possibility of tuning the NAND flash memory performance, reliabilityand power consumption acting on several tuning knobs such as the flash programming algorithm andthe flash error correcting code. However, to successfully exploit these degrees of freedom, it is mandatory toclearly understand the effect the combined tuning of these parameters have on the full NVM sub-system.This paper performs a comprehensive quantitative analysis of the benefits provided by the run-timereconfigurability of an MLC NAND flash controller through the combined effect of an adaptable memoryprogramming circuitry coupled with run-time adaptation of the ECC correction capability. The full nonvolatilememory (NVM) sub-system is taken into account, starting from the characterization of the low levelcircuitry to the effect of the adaptation on a wide set of realistic benchmarks in order to provide the readersa clear figure of the benefit this combined adaptation would provide at the system level.
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